Ethernet is a family of frame-based computer networking technologies for local area networks (LAN). It defines a number of wiring and signaling standards for the Physical Layer of the OSI networking model as well as a common addressing format and Media Access Control at the Data Link Layer.
The IEEE 802.3 standard, which is herein incorporated by reference, specifies the data format for Ethernet frames at various interfaces. For example, FIG. 82-3—PCS Transmit bit ordering, illustrates the required format of data blocks at the egress of the PCS.
FIG. 1 illustrates the required function of the MAC (Media Access Control) and PCS (Physical Coding Sublayer) as present in high-speed technologies such as 10 Gb/s (Giga-bits per second), 40 Gb/s, and 100 Gb/s Ethernet. The functions of the MAC and PCS are well known and are briefly described as follows.
In FIG. 1, the Ethernet data interface to the MAC and PCS may include a payload 100 consisting typically of 46 to 1500 bytes; a destination address 101 consisting typically of 6 bytes; a source address 102 consisting typically of 6 bytes; an optional 802.1Q tag and Ethertype 103 consisting typically of 6 or more bytes. These inputs are meant to illustrate and therefore the length and description of these Ethernet inputs do not limit the scope of the present invention. The Ethernet data bytes are input to the MAC and PCS on a transmit data bus 104 with a width w and output from the MAC and PCS on a receive data bus 105. The width w is specific to the particular implementation and may include additional control information as required (for example for maintenance and identifying the Ethernet data bytes).
In FIG. 1, the MAC and PCS circuit 106 functions to generate and decode the high speed Ethernet frame 122 format according to a specific Ethernet technology (for example 40 Gb/s or 100 Gb/s over fiber optics). The PCS function includes formatting and decoding the frame 122 correctly to be transmitted on 107 and received from 108 a number of physical lanes n, where n may be 1, 4, 10, or any other integer according to the specific Ethernet technology. The Ethernet frame 122 is encoded, scrambled, and striped across the n lanes 107 according to a predefined sequence by the PCS in the transmit direction. The PCS performs the reverse function in the receive direction.
The Ethernet frame 122 is constructed according to the applicable Ethernet specification clause, and typically includes the following groups of octets: a Start octet 110; a sequence of 6 Preamble octets 111; a Start of Frame Delimiter octet 112; a Destination Address of 6 octets 113; a Source Address of 6 octets 114; a Payload 116, 118 of 46 to 1500 octets total; a Frame Check Sequence 119 of 4 octets; and a Terminate character 120. There is also required to be an IPG (Inter Packet Gap) 121, 109 between occurrences of the Ethernet frame. The IPG consists of idle characters and is required to be an average of 12 octets minimum. Additionally, there are periodic Alignment Blocks 117, which may occur at any time during transmission, and are inserted between scheduled octets. They do not replace octets. For example, according to one issue of the Ethernet standard, a single Alignment Block is inserted into each lane every 16,383 blocks.
The receive function of FIG. 1 is substantially the reverse of the transmit function. That is to say, where the transmitter constructs and formats the Ethernet frame 122 from the incoming Ethernet data 104, the receiver decodes and disassembles the Ethernet frame 122 and sends Ethernet data 105 to the MAC client. Additional functions of the receiver such as the checking of the FCS 119 and the lane alignment process using the alignment block 117 are not within the scope of the present invention.
A challenge in generating the required sequence of octets in the transmit direction is to maintain the necessary minimum IPG when constructing the frame.
A more detailed view of the MAC and PCS circuits for the transmit direction is illustrated in FIG. 2, which shows a typical prior art implementation of the transmitter functions.
In FIG. 2, Ethernet data 200 from a MAC client is received by the MAC 203 module over a bus 204 of width w. The MAC frame generation circuit 205 functions to construct the Ethernet frame for transmission by prepending and appending information such as a header 206, FCS 207, and providing idle characters 208 between frames. The header consists of the Preamble and Start of Frame Delimiters as described by FIG. 1. It is then a function of the RS (Reconciliation Sublayer) 210 to format the Ethernet frame for transmission to the PCS module 215 over media independent interface (“xMII”) interface 213. The term xMII may refer to XGMII for 10 Gb/s Ethernet, XLGMII for 40 Gb/s Ethernet, or CGMII for 100 Gb/s Ethernet, depending on the Ethernet technology being implemented, or any other MII type of Ethernet interface as may be specified in future revisions of the IEEE 802.3 specification. The xMII interface consists of m lanes for Ethernet frame data, where m is typically 4 or 8 or a multiple of 8. Each lane transfers 8 bits in parallel (at one time). The MAC and PCS modules are clocked in different clock domains A and B.
The RS 210 typically includes a buffer circuit 209, which serves to temporarily store the octets comprising the Ethernet frame and then forward them to the xMII interface at the correct time according to a striping schedule. The RS circuit 210 arranges the Ethernet frame over the xMII interface in such a way that said frame will begin with the first octet of the header 206 in the first lane of the xMII interface 213. In so doing, the first octet of the preamble is replaced with a Start octet 212. The time for this to occur is controlled by the buffer 209 in response to the striping schedule. The remaining octets are transmitted over the xMII in a pre-determined sequence until the last octet of the FCS 207 has been transmitted. This will be followed by a Terminate octet 223 which replaces the first idle character of the inter packet gap.
Since the Ethernet frame may contain any integral number of octets (within certain pre-defined limits), the Terminate octet 223 may exist in any lane of the xMII interface. However, a rule exists that the Start octet shall occur in the first lane of the xMII interface. Therefore the required minimum 12 octets of IPG 208 may not be precisely achieved, since some idle octets may have to be inserted or deleted in order to present the next Start octet on the first lane of the xMII interface. Since a rule states that only an average of 12 octets minimum must be achieved, a Deficit Idle Counter (DIC) 211 is used to keep track of the idle octets inserted or deleted. Information from the DIC controls the readout schedule from the buffer 209. Thus the xMII data rate will be the same as the MAC data rate on average. The DIC 211 is adjusted depending on which lane the start character has been shifted to and the terminate location.
It is noted that in some prior art embodiments, the xMII interface is not a physical interface, but exists logically within an integrated circuit.
Continuing with FIG. 2, the transmit PCS 215 functions to arrange the m xMII data lanes 213 for transmission over a physical interface 221 consisting of n lanes. The main functions include encoding, scrambling, lane distribution 219, and alignment code insertion 220. Since the insertion of alignment codes 218 results in extra bandwidth, a rate adapting FIFO 217 is required to periodically add or delete idle characters. Furthermore, since the MAC processing clock 202 and PCS processing clock 216 may be different, the rate adapting FIFO 217 also serves to add or delete idle characters in order to maintain uninterrupted data flow to the physical medium, where data includes the Ethernet frame and idle characters. It is noted that idle characters are required to be deleted or inserted by the PCS in groups of 8 (one block). This ensures that the Start character for an Ethernet frame will remain at the start of a PCS lane.
The transmitted Ethernet frame 222 including all control characters and the IPG 223 (all of which were formatted by the PCS) are striped across the n lanes of the physical medium 221 in a predefined sequence which is known to those skilled in the art. The value of n is typically 1, 4, or 10 depending on the type of physical interface.